1. Field of the Invention
The present invention relates to a circuit for generating internal voltage in a semiconductor device, and more particularly, to a structure of a circuit for generating a programming voltage and an erase voltage used for programming and erasing in a non-volatile semiconductor memory device.
2. Description of the Background Art
FIG. 1A schematically shows a sectional structure of a memory cell of a flash memory, and FIG. 1B shows an electrical equivalent circuit thereof. Referring to FIG. 1A, a flash memory cell includes high concentration impurity regions 102a and 102b formed on the surface of a semiconductor substrate 100, a floating gate 108 formed on a channel region 104 between impurity regions 102a and 102b with a thin gate insulating film 106 thereunder, and a control gate 112 formed on floating gate 108 with an interlayer insulating film 110 thereunder. Semiconductor substrate 100 may be an epitaxially grown layer or a well region. The flash memory cell includes a structure of a MOS (insulation gate type) transistor having a two layered gate structure. Impurity region 102a provides a drain region, and impurity region 102b provides a source region. In FIG. 1A, impurity regions 102a and 102b are connected to a drain electrode D and a source electrode S, respectively. Control gate 112 is connected to a control gate electrode CG.
The flash memory cell shown in FIG. 1A stores a binary data of "0" and "1" according to the amount of charge stored in floating gate 108. Floating gate 108 is in an electrically floating state so that data can be stored in a non-volatile manner.
The flash memory includes a memory cell array having a plurality of such memory cells arranged in a matrix. Referring to FIG. 1B, a flash memory cell in a memory cell array has its control gate electrode CG connected to a word line WL, its drain electrode D connected to a bit line BL, and its source electrode S connected to a source line SL. A row of memory cells are connected to the word line WL, and a column of memory cells are connected to the bit line BL. The source line SL is provided in common to a predetermined number of memory cells (sector unit, page unit).
The injection of charge (electrons) into the floating gate of a flash memory cell and the draw of charge (electrons) from the floating gate is carried out in an electrical manner set forth in the following.
The injection operation of electrons into a floating gate will first be described with reference to FIG. 2. Referring to FIG. 2, a voltage of approximately 6 V is applied to the drain electrode D, and a high voltage of approximately 12 V is applied to the control gate CG. The source electrode S is set to 0 V. Under this state, a channel is formed between impurity regions 102a and 102b by the high voltage applied to the control gate electrode CG to cause a current flow. The carriers in this channel current are accelerated to become hot carriers by the drain electric field of high intensity formed in the proximity of impurity region 102a. These hot carriers become avalanche hot carriers by impact ionization, Electrons of these avalanche hot carriers are accelerated towards floating gate 108 to be stored therein by the high voltage applied to the control gate electrode CG. This state in which electrons are stored in floating gate 108 is called "a programmed state", and corresponds to the state where data "0" is stored.
The operation of drawing electrons from a floating gate is carried out as shown in FIG. 3. Referring to FIG. 3, the drain electrode D is set to an electrically floating state, a high voltage of approximately 12 V is applied to the source electrode S, and the control gate electrode CG is set to 0 V. In such a state, a high electric field is applied between floating gate 108 and impurity region 102b to generate. Fawler-Nordheim type tunnel current, whereby electrons stored in floating gate 108 are drawn towards impurity region 102b. This state where electrons are drawn out from floating gate 108 is called "an erased state", and corresponds to the state of storing data "1".
In the programmed state where electrons are stored in floating gate 108, a channel is not easily formed in the channel region, whereby the threshold voltage Vth is shifted to a higher value to result in a threshold voltage of V2 as shown in FIG. 4.
In the state where electrons are drawn out from floating gate 108, a channel is easily formed in the channel region so that the threshold voltage is shifted to a lower value of V1 as shown in FIG. 4.
In reading out data, the source electrode S is set to ground potential of 0 V, the drain electrode D is supplied with a read out voltage of approximately 1-2 V, and the control gate electrode CG receives a voltage of approximately 5 V. The voltage value (5 V) applied to the control gate electrode CG at the time of read out is between the threshold voltages V1 and V2 shown in FIG. 4. In accordance with the information stored in the flash memory cell, current flows or not flows from impurity region 102a to impurity region 102b. Data read out is carried out by identifying the presence/absence of this current.
In the erasing operation of the above-described flash memory cell, a high voltage of approximately 12 V is applied to the source region (impurity region 102b). The memory cell suffers from limitations set forth in the following in this case. That is to say, the source impurity region requires a high breakdown voltage structure, and the source impurity region is increased in depth. Therefore, the gate length of the memory cell can not be reduced in order to prevent punch through, so that the memory cell size can not be reduced.
Furthermore, because a high voltage is applied to the source impurity region, a high electric field is generated in the proximity of the source impurity region as shown in FIG. 5. As a result, hot holes are generated to be trapped in a tunnel film (a very thin insulating film between source impurity region 102b and floating gate 108). The holes trapped in this tunnel insulating film reduces the number of programming times. Also, if the holes stored in the insulating film exceeds a predetermined amount, the insulating film is destructed.
Because the substrate current generated at the source impurity region is great in the erasing operation, the high voltage required for erasing can not be generated using an on-chip boosting circuit. A high voltage generating circuit must externally be provided.
A method of applying negative voltage to the control gate in an erasure operation is proposed to provide a device that can be operated by a 5 V only power source, has a large storage capacity, and that has an increased number of times of programming.
FIG. 6 shows the voltage applying conditions in such a negative gate voltage system. In the method shown in FIG. 6, a negative voltage of approximately -10 V is applied to the control gate electrode CG, a voltage of approximately 5 V is applied to the source electrode S, and the drain electrode D is set to an electrically floating state. In such a state, electrons are drawn from floating gate 108 towards source impurity region 102b via tunnel insulating film 106 by a Fawler-Nordheim type tunnel current because a high voltage of approximately 15 V is applied between source impurity region 102b and control gate 112 as in a conventional case.
FIG. 7 shows another voltage applying condition according to the negative gate voltage method. In the negative gate voltage method shown in FIG. 7, a power supply voltage of 5 V is applied to a semiconductor substrate (P well) 100, and a negative voltage of approximately -11 to -14 V is applied to the control gate electrode CG. The source electrode S and the drain electrode D respectively attain an electrically floating state. In this state, electrons are drawn from floating gate 108 towards substrate 100 by a Fawler-Nordheim type tunnel current via a tunnel insulating film (gate insulating film 106).
As described above, Fawler-Nordheim type tunneling current is used in the source-gate erasing method shown in FIG. 6 and in the substrate erasing method shown in FIG. 7. Although the voltage required for erasing is a high voltage such as 15 V-20 V in comparison with the source erasing method applying a high voltage of approximately 12 V to the source, a high breakdown voltage structure is not required since a high voltage is not applied to the source impurity region, and the amount of generated hot holes is also reduced.
Because a high voltage is not applied to the source in the gate negative voltage erasing method in which a negative voltage is applied to the control gate, the substrate current generated at the source impurity region is reduced. Therefore, the current required in an erasing operation is only the Fawler-Nordheim type tunnel current for drawing electrons stored in the floating gate. Thus, the current required in an erasing operation is reduced, so that the negative voltage to be applied to the control gate can be produced with an on-chip voltage down converter. This voltage down converter has a structure similar to a charge pumping circuit used in a boosting circuit for generating a high voltage to be applied at the time of programming in conventional art. Therefore, a flash memory of an external 5 V only power source is implemented by this negative gate voltage applying method. However, this negative gate voltage method requires provision of a positive voltage at the time of data read out and programming operations and a negative voltage at the time of erasing operation to the control gate.
FIG. 8 schematically shows the entire structure of a conventional flash memory. Referring to FIG. 8, a flash memory includes a memory cell array 200 having a plurality of memory cells MC arranged in a matrix of rows and columns, and an address latch 202 for latching applied address signals A0-An for generating an internal address signal. Memory cell array 200 includes a word line WL connected to memory cells MC of 1 row, a bit line BL connected to 1 column of memory cells, and a source line SL to which a predetermined number of memory cells MC are coupled in common. In FIG. 8, only one memory cell MC is typically shown. Memory cell array 200 may have a structure in which a predetermined number of memory cells of one word line WL are erased in the unit of a sector.
The flash memory further includes an X decoder 204 for decoding an internal row address signal from address latch 202 to generate a signal for selecting a corresponding word line, a word line driver 206 for applying a predetermined voltage to a corresponding word line according to a word line select signal from X decoder 204, a Y decoder 208 for decoding an internal column address signal from address latch 202 for generating a signal to select a corresponding column in memory cell array 200, and a Y selection gate 212 responsive to a column select signal from Y decoder 208 to connect a corresponding bit line BL to internal data buses 210a and 210b. Data bus 210a transmits read out data, and data bus 210b transmits program data. Data buses 201a and 210b may be the same data bus.
The flash memory further includes a program/erase control circuit 214 responsive to externally applied control signals CE, OE, and WE for generating a control signal required for various operations, a Vpp/Vcc generation circuit 216 for generating a high voltage Vpp or an operating power supply voltage Vcc from an external power supply voltage Vcc under the control of program/erase control circuit 214, a negative voltage generating circuit 218 for generating a negative voltage of a predetermined potential level under the control of program/erase control circuit 214, and a source potential generating circuit 220 for generating a voltage to be supplied to a source line SL under the control of program/erase control circuit 214.
Program/erase control circuit 214 determines the address signal latch timing of address latch 202, the decoder operation timing of X decoder 204, and the decoder operation timing of Y decoder 208. A signal CE is a chip enable signal instructing that this flash memory is selected. A signal OE is an output enable signal indicating that a data read out operation mode is instructed. A signal WE is a write enable signal indicating that a data programming operation mode is instructed. Program/erase control circuit 214 generates a control signal required for data erasing and programming of a memory cell when signals CE and WE are both active.
The flash memory further includes a sense amplifier 222 for detecting and amplifying the data applied on data bus 210a, a programming circuit 224 for providing program data to data bus 210b, and an input/output buffer 226 for carrying out data input/output with an external device of the memory. Sense amplifier 222 has a structure of a current detection type sense amplifier to generate and provide to input/output buffer 226 an internal read out data according to whether current flows or not in a selected column, i.e. a selected bit line. Programming circuit 224 generates a program data according to an internal program data from input/output buffer 226 to apply a predetermined voltage corresponding to program data to a selected bit line.
The output of sense amplifier 222 is supplied to program/erase control circuit 214 for identifying whether data is reliably erased or a desired program data is written properly in an erasing operation and a programming operation.
In an erasing operation, negative voltage generating circuit 218 is activated to generate a predetermined negative voltage under the control of program/erase control circuit 214. X decoder 204 decodes an internal row address signal from address latch 202. Word line driver 206 transmits the negative voltage from negative voltage generating circuit 218 to a selected word line.
During this erase operation, source potential generating circuit 220 generates and transmits to the source line SL a signal of the power supply voltage Vcc level under the control of program/erase control circuit 214. Y decoder 208 has not carried out a decode operation, and all the selection gates of Y selection gate 212 (provided corresponding to each bit line) all attain a non-conductive state. Thus, the bit line BL attains an electrically floating state. Under this state, an erase operation is carried out in a predetermined number of memory cells of 1 row or 1 sector connected to the selected word line.
Although an erase operation is described according to a source-gate erase method, the erase operation may be carried out according to a gate-substrate erase method. In the case of a gate-substrate erase method, source potential generating circuit 220 sets the source line SL at an electrically floating state to apply power supply voltage Vcc to the substrate of the memory cell at the time of erasure. This substrate voltage supplying circuit is normally provided independently of source potential generating circuit 220.
In general, a data program operation is carried out after an erase operation. In this case, negative voltage generating circuit 218 is set to an inactive state. Source potential generating circuit 220 sets the source line SL to the level of ground potential GND. Program circuit 224 generates a high voltage of approximately 6 when the program data from input/output buffer 226 is "0". Vpp/Vcc generating circuit 216 generates a high voltage Vpp, which is supplied to word line driver 206 (this signal transmission path is not shown). In data programming, X decoder 204 and Y decoder 208 both execute a decoding operation. A high voltage Vpp is applied on a selected word line, and a relatively high voltage from program circuit 224 is generated onto the selected bit line. As a result, data "0" is written into the memory cell. In a memory cell to which data "1" is to be written, the potential of the corresponding bit line is 0 V which is a level where injection of electrons to a floating gate is not normally carried out and an erased state is maintained. The erased state corresponds to data "1".
In data read out operation, program/erase control signal 214 responds to a signal OE to inhibit the high voltage generation operation of Vpp/Vcc generating circuit 216. Vpp/Vcc generating circuit 216 generates power supply voltage Vcc in this case. Similarly, negative voltage generating circuit 218 is made inactive. Source potential generating circuit 220 connects the source line SL to ground potential GND. Under such a state, the selection operation of memory cells is executed according to an address signal latched in address latch 202, whereby a signal of power supply voltage level Vcc is transmitted to the selected word line via word line driver 206. A low read out voltage (approximately 1-2 V) from the read out voltage generating circuit in sense amplifier 222 is applied to the bit line BL. Sense amplifier 222 detects a flow of current to generate and provide to input/output buffer 226 data.
In the foregoing, program/erase control circuit 214 is described to determine the operation timings of address latch 202, Y decoder 208, and X decoder 204 at the time of data read out. As an alternative, program/erase control circuit 214 may not carry out any control operation, and address latch 202, X decoder 204, and Y decoder 208 may carry out static processings of applied signals.
FIG. 9 specifically shows a structure of the Vpp/Vcc generating circuit shown in FIG. 8. Referring to FIG. 9, the Vpp/Vcc generating circuit includes a ring oscillator 802 activated in response to a control signal .PHI.1 for carrying out an oscillation operation at a predetermined cycle, a charge pump 804 for carrying out a charge pump operation according to an oscillation signal from ring oscillator 802 to generate a predetermined high voltage Vpp, and a selection circuit 806 for selecting and providing either a high voltage Vpp from charge pump 804 or a power supply voltage Vcc
Ring oscillator 802 is normally implemented by inverter circuits of an odd number of stages. The oscillation period of ring oscillator 802 is determined by the number of the stages of the inverter circuits and the delay time in each inverter circuit. Charge pump 804 includes a capacitor and a diode. By a charge injection operation by the capacitance coupling of the capacitor, a high voltage Vpp of a predetermined level (for example 12 V) is generated from power supply voltage Vcc.
Selection circuit 806 includes a p channel MOS (insulation gate type) transistor 810 responsive to a control signal .PHI.A to pass high voltage from charge pump 804, a p channel MOS transistor 814 responsive to a control signal .PHI.B to pass power supply voltage Vcc, and an n channel MOS transistor 812 provided between transistors 810 and 814 for receiving power supply voltage Vcc at its gate. Voltage Vpp/Vcc of a predetermined level is generated from the connection node of transistors 810 and 812. "Vpp/Vcc" indicates either high voltage Vpp or power supply voltage Vcc.
Control signals .PHI.1, .PHI.A and .PHI.B are generated from program/erase control circuit 214 shown in FIG. 8. In a programming operation mode requiring provision of high voltage to the control gate of a memory cell, control signal .PHI.A attains a L level (logical low), whereby high voltage Vpp is selected from charge pump 804. In an erase operation and in normal data read out operation, the control signal .PHI.B attains a L level, whereby power supply voltage Vcc is selected. In this erase operation mode and normal read out operation mode, the control signal .PHI.1 becomes inactive so that ring oscillator 302 does not carry out an oscillation operation. The output of charge pump 804 is set to the level of ground potential GND or power supply voltage Vcc. Under such a state, the control signal .PHI.A attains a H level (logical high) to turn off transistor 810.
Transistor 812 receives power supply voltage Vcc at its gate to function as a protective resistance element to prevent high voltage Vpp through transistor 810 from being applied to transistor 814. The control signal .PHI.B attains a H level in a programing operation mode to turn off transistor 814. Here, a H level indicates the power supply voltage Vcc level.
FIG. 10 shows an example of a structure of the X decoder and the word line driver shown in FIG. 8. Referring to FIG. 10, X decoder 204 includes a unit decoder circuit 250 provided corresponding to each word line. This unit decoder circuit 250 includes a structure of an NAND circuit to provide a L signal of 0 V level when attaining a selected state.
Word line driver 206 includes a Vpp switch 252 and a negative voltage switch 254 provided corresponding to unit decoder circuit 250. Vpp switch 252 provides a signal of the level of voltage Vpp/Vcc when the output of unit decoder circuit 250 is "L" indicating a selected state. When the output of unit decoder circuit 250 is H (power supply voltage Vcc level) indicating a non-selected state, Vpp switch 252 provides a signal of ground potential level GND.
In an erase operation mode, negative voltage switch 254 provides a signal of power supply voltage level Vcc (5 V) when the output of unit decoder circuit 250 attains a L level indicating a selected state, and provides a negative voltage Vng of a predetermined level, for example -10 V, when the output of unit decoder circuit 250 attains a H level indicating a non-selected state. In normal data read out mode and programming mode, negative voltage Vng is not generated, and is set to the level of ground potential GND.
Word line driver 206 further includes an n channel MOS transistor 256 responsive to an erase mode designating signal /.PHI.E for transmitting an output of unit decoder circuit 250 to Vpp switch 252, a p channel MOS transistor 258 responsive to a signal .PHI.E for transmitting the output of Vpp switch 252 to a word line WL, an n channel MOS transistor 260 responsive to a signal .PHI.E for transmitting the output of unit decoder circuit 250, an inverter circuit 262 for inverting and transmitting to negative voltage switch 254 a signal transmitted from transistor 260, an n channel MOS transistor 264 responsive to a signal .PHI.E for transmitting an output of negative voltage switch 254, an n channel MOS transistor 266 responsive to an output of transistor 264 for transmitting negative voltage Vng to a word line WL, and an n channel MOS transistor 265 responsive to a signal /.PHI.E for connecting the gate of transistor 266 to ground potential GND.
The erase mode designating signal .PHI.E attains a H level of power supply voltage Vcc in erase operation mode. The signal .PHI.E is set to the level of ground potential GND in operations other than the erase mode operation, i.e. in normal data read out mode and programming mode. The signal /.PHI.E is a complementary signal of the erase mode designating signal .PHI.E. The signal /.PHI.E attains a level of ground potential GND in an erase mode operation, and a level of power supply voltage Vcc in other operation modes.
Word line driver 206 further includes an inverter circuit 272 receiving an output of unit decoder circuit 250, a p channel MOS transistor 268 for receiving an output of inverter circuit 272 at its gate, and an n channel MOS transistor 270 for receiving an output of unit decoder circuit 250 at its gate. Transistors 268 and 270 are provided in series between the word line WL and ground potential GND. When the output of unit decoder circuit 250 attains a H level and a corresponding word line WL attains an non-selected state, transistors 268 and 270 are turned on simultaneously, whereby the potential of the word line WL is set to the level of ground potential GND. When the corresponding word line WL attains a selected state, transistors 268 and 270 are both turned off. In this case, the gate voltage of transistor 268 attains the level of power supply voltage Vcc and transistor 268 is turned off even if a negative voltage Vng is transmitted to the word line WL because p channel MOS transistor 268 is coupled to the word line WL. This reliably prevents the negative voltage on the word line WL from being coupled to ground potential GND. The operation thereof will be described hereinafter.
In an erase operation mode, the signal .PHI.E attains a H level of power supply potential Vcc, and the signal /.PHI.E attains a L level of ground potential GND. In this case, the output of unit decoder circuit 250 is transmitted to negative voltage switch 254. Negative voltage switch 254 provides an H signal of power supply voltage Vcc when the output of inverter circuit 262 attains a H level (the level of the power supply potential Vcc). This turns on transistor 266, whereby a negative voltage Vng is transmitted on the word line WL. Here, transistors 268 and 270 are both turned off because the output of inverter circuit 272 attains a H level of power supply voltage Vcc and the output of unit decoder circuit 250 attains a L level of ground potential GND. Thus, the potential of the selected word line WL is reliably set to the level of negative voltage Vng.
When the output of unit decoder circuit 250 attains a H level (power supply voltage Vcc), the outputs of inverter circuits 262 and 272 both attain a L level (ground potential GND). In this case, negative voltage switch 254 generates a negative voltage Vng which is supplied to the gate of transistor 266. Transistor 266 is turned off because the potential between the gate and the source is identical, so that the negative voltage Vng is not transmitted to the word line WL. Here, transistors 268 and 270 both are turned on, whereby the potential of word line WL is set to the level of ground potential GND.
In data read out mode and programming mode operation, the signal .PHI.E attains a L level of ground potential GND, and the signal /.PHI.E attains a H level of power supply voltage Vcc. As a result, the output of unit decoder circuit 250 is transmitted to Vpp switch 252. Transistor 265 responds to the signal /.PHI.E to conduct, whereby the gate potential of transistor 266 is fixed to the level of ground potential GND. In this case, the negative voltage Vng is not generated (is at GND level). Thus, transistor 266 is reliably turned off.
Vpp switch 252 generates a signal of voltage Vpp/Vcc level when the output of unitary decoder circuit 250 attains a L level (ground potential GND). p channel MOS transistor 258 receives a signal of ground potential GND at its gate. As a result, the voltage Vpp/Vcc from Vpp switch 252 is transmitted to the word line WL, whereby the potential of the word line WL rises to the level of Vpp/Vcc. Here, the output of inverter circuit 272 attains a H level (power supply voltage Vcc), and p channel MOS transistor 268 is turned on when the potential of the word line WL attains a level of high voltage Vpp. Because n channel MOS transistor 270 receives a signal of ground potential GND at its gate also in this case, n channel MOS transistor 270 is reliably turned off, whereby the level of potential Vpp of the word line WL is reliably maintained.
When the output of unit decoder circuit 250 attains a H level, Vpp switch 252 provides a signal of ground potential GND. In this case, p channel MOS transistor 258 is turned off. Transistor 268 and 270 are both turned on, whereby the potential of the word line WL is fixed to the level of ground potential GND. The structures of the negative voltage switch and the Vpp switch will be described hereinafter.
FIG. 11 specifically shows a structure of a Vpp switch. Referring to FIG. 11, a Vpp switch 252 includes inverter circuits 70 and 72 cascade-connected in two stages for receiving an input signal IN, and an n channel MOS transistor 74 for passing the output of inverter circuit 72. Power supply voltage Vcc is applied to the gate of transistor 74. Transistor 74 has a protective resistance function according to the characteristics of a MOS transistor passing only a voltage of a gate voltage less the threshold voltage.
Vpp switch 252 further includes a p channel MOS transistor 76 and an n channel MOS transistor 78 connected in a complementary manner for receiving an output of inverter circuit 72 at its respective gates via transistor 74. p channel MOS transistor 76 receives voltage Vpp/Vcc at its source. n channel MOS transistor 78 has its source connected to ground potential GND. Vpp switch 252 further includes a p channel MOS transistor 80 for receiving an output signal OUT at its gate to transmit voltage Vpp/Vcc to the gates of transistors 76 and 78. The operation thereof will be described hereinafter.
When an input signal IN attains a H level of 5 V, transistor 78 is turned off, and transistor 76 is reduced in conductance. As a result, the output signal OUT is discharged by transistor 78, whereby the potential level thereof is reduced. In accordance with reduction of the potential level of the output signal OUT, transistor 80 goes to an ON state to charge the gates of transistors 76 and 78 to the level of voltage Vpp/Vcc. When the gates of transistors 76 and 78 attain the voltage level of Vpp/Vcc, transistor 76 is completely turned off, whereby the output signal OUT attains a L level of 0 V. Even if the gates of transistors 76 and 78 attain a level of high voltage Vpp, this high voltage Vpp will not be transmitted to the output portion of inverter circuit 72 on account of the decoupling function of transistor 74. Thus, stability of the circuitry can be achieved.
When the input signal IN attains a L level of 0 V, transistor 76 is turned on and transistor 78 is turned off. As a result, the output signal OUT is raised to the level of Vpp/Vcc. In accordance with the rise of the output signal OUT, transistor 80 is turned off. The determination of which of voltages Vpp and Vcc is applied is made depending on the operation mode. High voltage Vpp is applied in a program mode operation, and voltage Vcc is applied in a normal data readout mode operation.
FIG. 12 specifically shows a structure of a negative voltage switch 254. The structure of this negative voltage switch shown in FIG. 12 is described in ISSCC 92 SLIDE SUPPLEMENT, pp. 114-115, for example. Referring to FIG. 12, a negative voltage switch 254 includes an inverter circuit 1 for receiving an input signal IN, a p channel MOS transistor 2 for receiving the output of inverter circuit 1 by its gate for charging an output signal line 8 to the level of power supply voltage Vcc, a depletion type P channel MOS transistor 3 having its gate connected to a node N100 and its source connected to output signal line 8, and an n channel MOS transistor 4 having its gate receiving the output of inverter circuit 1, its drain connected to the drain of transistor 3, and its source connected to the level of ground potential GND. The substrate of depletion type p channel MOS transistor 3 and p channel MOS transistor 2 are coupled to power supply voltage Vcc. Transistor 3 is turned on at the time of normal operation to function as a load resistor.
Negative voltage switch 254 further includes a p channel MOS transistor 5 responsive to the potential on output signal line 8 for charging node N10 to the level of the voltage applied to node N102, an n channel MOS transistor 6 responsive to a signal on output signal line 8 for discharging node n10 towards the level of negative voltage Vng, and an n channel MOS transistor 7 responsive to the potential on node N10 for charging output signal line 8 towards the level of negative voltage Vng. The operation thereof will be described hereinafter. In the following description, it is assumed that the power supply voltage Vcc is 5 V, the negative voltage Vng is -10 V, and the ground potential GND is 0 V.
In an erase mode operation, 5 V is applied to nodes N100 and N102. When the input signal IN attains a level of 5 V (when the output of inverter circuit 262 attains a H level in FIG. 10), the output of inverter circuit 1 becomes 0 V. This causes transistor 2 to be turned on and transistor 4 to be turned off, whereby output signal line 8 is discharged to 5 V of the power supply voltage Vcc level. In accordance with the rise of the potential of the output signal line 8, transistor 5 is turned off and transistor 6 is turned on. In response to turn on of transistor 6, node N10 is discharged towards negative voltage Vng, and transistor 7 changes to an OFF state. As a result, output signal line 8 is maintained at 5 V, whereby the output signal OUT attains a H level of 5 V.
When the input signal IN attains a level of 0 V (when the output of decoder circuit 250 attains a H level in FIG. 10), the output of inverter circuit 1 becomes 5 V. Under such a state, transistor 2 is turned off and transistor 4 is turned on. Transistor 3 is slightly turned on by the potential of node N100 attaining a level of 5 V. This causes the output OUT on output signal line 8 to be discharged to 0 V. In this case, output signal OUT gradually decreases in level on account of the function of the load resistance of depletion type transistor 3. In accordance with reduction of the potential level of the output signal OUT, transistor 5 gradually attains an 0N state, whereby transistor 6 is reduced in conductance (due to the reduced potential difference between the gate and source of transistor 6). As a result, node N10 is charged via transistor 5, whereby the potential of node N10 rises gradually. In response to the potential level of node N10 gradually rising from -10 V, transistor 7 is gradually turned on, whereby the potential of output signal 8 is discharged towards negative voltage Vng (-10 V). The reduction of the potential level of output signal OUT on output signal line 8 is fed back to the gates of transistors 5 and 6. The potential level of node N10 eventually rises to the level of 5 V, whereby transistor 7 is completely turned on, and the output signal OUT eventually takes a level of -10 V.
Transistor 3 is turned off when the output signal OUT attains the level of approximately 0 V to 1 V, depending upon the threshold voltage. More specifically, the output signal OUT is initially discharged to the level of 0 V by transistors 3 and 4. As the level of the output signal OUT is further reduced, discharge is continued via transistor 7, and the signal OUT eventually attains the level of the negative voltage (-10 V). Because transistors 3 and 4 are turned off under this state, the output signal OUT is maintained at the level of -10 V.
More specifically, the negative voltage switch 254 shown in FIG. 12 generates an output signal OUT of 5 V when the input signal IN attains the level of 5 V, and generates an output signal of -10 V when the input signal IN attains the level of 0 V.
In a normal data read out mode operation and a program mode operation, the negative voltage switch having the structure shown in FIG. 12 will not function. A voltage of 0 V is applied to nodes N100 and N102, and the negative voltage Vng is set to 0 V (the operation of the negative voltage generating circuit is suppressed). In such a state, transistor 3 is deeply turned on. The conductance thereof is great. Transistors 5, 6 and 7 do not function because the potential of node N102 is 0 V. When the input signal IN attains the level of 5 V, output signal line 8 is charged via transistor 2, whereby the output signal OUT attains the level of 5 V. When the input signal IN attains the level of 0 V, transistor 4 is turned on, and output signal line 8 is discharged towards ground potential GND. As a result, the output signal OUT attains a level of 0 V. In other words, this circuit functions as a buffer circuit.
In accordance with the above-described negative gate voltage method in which a negative voltage is applied to the control gate, an on-chip boosting circuit (or a charge pump circuit) can be used to realize a flash memory that can operate with an external 5 V unitary power source.
However, because the negative voltage switch generates a voltage of 5 V and -10 V as shown in FIG. 12, a voltage as high as 15 V is applied between the source and drain of some transistors. For example, when the input IN attains a level of 0 V, inverter circuit 1 has an output of 5 V which is provided to the gate of transistor 2 in FIG. 12, for example. Under such a state, transistor 2 is turned off, but the output signal OUT is -10 V. Therefore, a voltage of 15 V is applied between the source and drain of transistor 2.
Transistors are reduced in size as the storage capacity of a flash memory is increased. When a high voltage is applied to a scaled-down transistor, various problems occur such as avalanche due to concentrated electric field between the drain and gate, damage of the gate insulating film, and generation of punch through. That is to say, the breakdown voltage of a transistor is reduced as its size is reduced. Therefore, there is a problem that the negative voltage switch can not be operated in a stable manner when scaling down is advanced in a flash memory of a large capacity.
This problem of the breakdown voltage in a transistor is also seen in the Vpp switch shown in FIG. 11 (high voltage Vpp is approximately 12 V).